📆 Course Schedule

Note

This schedule is subject to change as appropriate.

Last Updated: 13 September 2024

Lesson	Topic	Reading	Due
1	Lec 1: Intro, VHDL, Digital Systems Design	1.1-1.7
2	Lec 2: Digital Systems, hierarchical design, testbench	2.1, 2.2.1, 2.2.2	HW1
3	Lec 3: Combinational elements, unsigned, constraints file, synthesis	3.5.4, 4.2.3, 4.3.1	HW2
4	Lec 4: Sequential elements	5.1,5.2,5.7,5.8	HW3
5	Lec 5: Combinations of elements, Lab intro	7.2	HW4
6	Lab 1: VGA Synchronization		HW5
7	Lab 1: VGA Synchronization		Lab1-GateCheck1
8	Lab 1: VGA Synchronization		Lab1-GateCheck2
9	Finite State Machines	10.2.1, 10.3.2, 10.4, 10.6.1	Lab1-Final
10	Datapath and Control	11.1, 11.2, 14.4.2
11	Datapath and Control	11.5	HW7
12	Datapath and Control, Lab intro		HW8
13	Lab 2: Data acquisition, storage, and display		HW8b
14	Lab 2: Data acquisition, storage, and display		Lab2-GateCheck1
15	Lab 2: Data acquisition, storage, and display		Lab2-GateCheck2
16	Lab 2: Data acquisition, storage, and display		Lab2-GateCheck3
17	Review and Lab 2: Data acquisition, storage, and display
18	GR 1		Lab2-Final
19	Soft CPU		HW9
20	Soft CPU		HW10
21	Soft CPU	[Final Project Ideas	https://youtube.com]
22	Lab 3: Oscilloscope Control
23	Lab 3: Oscilloscope Control
24	Lab 3: Oscilloscope Control		Lab3-GateCheck1 Lab3-GateCheck2
25	Lab 3: Oscilloscope Control		Lab3-GateCheck3
26	Lab 3: Oscilloscope Control		Lab3-Final
27	Direct Digital Synthesis		HW13
28	Lab 4: Function Generator
29	Lab 4: Function Generator		Lab4-GateCheck1
30	Lab 4: Function Generator		Lab4-GateCheck2
31	GR 2
32	Lab 5: Final Project
33	Lab 5: Final Project
34	Lab 5: Final Project
35	Lab 5: Final Project
36	Lab 5: Final Project
37	Lab 5: Final Project
38	Lab 5: Final Project		Lab 5: Final Project
39	Final Project Presentation/Demo Day
40	Final Report		Lab 5: Final Report