📆 Course Schedule

📆 Course Schedule#

Note

This schedule is subject to change as appropriate.

Last Updated: 2 January 2026

Lsn

Topic

Reading Assignment

Homework: default due BOC

Handouts

1

Course Introduction

1.1 - 1.6

Skills Review (due lsn 4)

  • lesson slides are on course TEAMs site
  • Syllabus

2

Skill Review Day [Single-Cycle RISC-V architecture]

Microarchitecture

CPH1

3

Trends in Computer Technology

1.6 - 1.9

CPH2

  • lesson slides are on course TEAMs site

4

Price vs Performance

1.8 - 1.9

skills Review

  • lesson slides are on course TEAMs site

5

Performance, Metrics, Benchmarks, Amdahl’s Law

1.10-1.12; benchmarking articles in CPH4

CPH4

6

Metrics and Benchmarks

1.10-1.12; A.1 - A.9; Quiz Today?

CPH5

  • lesson slides are on course TEAMs site

7

Instruction Set design, memory addressing, operations, operands

A.1 - A.9

CPH6

8

CISC vs RISC Debate

CPH7

RISCvsCISCDebate

9

Compiler Technology, RISC-V architecture

A.8 - A.9

Sorry, no CPH8 this year

  • lesson slides are on course TEAMs site

10

Pipeline Introduction & Hazards

C.1 - C.5, C.8

CPH9

  • lesson slides are on course TEAMs site

11

Data Hazards, Control Hazards, Pipeline Implementation, ILP

C.3 - C.5, C.8, 3.1

CPH10

12

Overcoming Hazards: forwarding and branch fix

C.3 - C.5, C.8, 3.1

CPH11

13

Work on RISC-V Exercise (due lesson 13)

CPH12

RISCV_Assignment due lesson 13

14

Dependencies: Data, Name, Control

C.7, 3.4

Sorry, no CPH13 this year

15

Overcoming Hazards - Dynamic Scheduling & Tomasulo’s Algorithm

CPH14

16

Tomasulo’s Algorithm & Dynamic Branch Prediction

3.3, 3.6

CPH16; Sorry, no CPH15 this year

  • lesson slides are on course TEAMs site

17

Branch Target Buffers, Speculation

3.7 - 3.9, 3.12-3.14, 5.8

CPH17

18

GR#1

19

Final Project Stage1

Stage1 Assignment

20

Final Project Stage1

Final Project Stage 1, due lesson 21

Stage1 Assignment

21

VLIW & Superscalar, SIMD?

  • lesson slides are on course TEAMs site

skip

Data-Level Parallelism in Vector, SIMD, GPU Architectures

22

Memory Hierarchy Design: Cache Memory

2.1, B.1, B.2

CPH20

23

Memory Hierarchy Design: Cache Memory

2.1, B.1, B.2

CPH21

24

Improving Cache Performance; QUIZ TODAY!

2.1, B.1, B.2, B.3, B.4

CPH22

  • lesson slides are on course TEAMs site

25

Improving Cache Performance; Main Memory

2.2, B.3, B.4

CPH25

26

Final Project Stage2

Stage2 Assignment

27

Final Project Stage2

Final Project Stage 2, due lesson 27

Stage2 Assignment

28

Virtual Memory

2.4

CPH26

  • lesson slides are on course TEAMs site

29

Storage Devices: RAID

D.1 - D.3; skim D.4, D.7

CPH27

30

I/O Interfacing & Performance, Interconnection Networks

F.1, F.2; skim F.5, F.6

CPH29

31

LAN Topologies, Routers/Gateways, Flynn’s Taxonomy; Memory Arch

F.1, F.2; skim F.5, F.6

CPH30

32

Introduction to Multiprocessors

page 10; 5.1

33

Symmetric Shared Memory Architectures

5.2

CPH31

34

Distributed Memory Coherence

5.4 (maybe 5.5, 5.6)

CPH32

skip

Clusters, Example: Google Cluster, LAN Example

6.5 - 6.8; L29 Google Arch.pdf

GoogleArchitecture

35

GR#2

skip

Lead a 6-minute discussion on computing laws

  • Moore’s Law
  • Metcalfe’s Law
  • Yules Law
  • Hoff’ Law
  • Evan’s Law
  • Law of Digitiplication

36

Final Project Stage3

Stage3 Assignment

37

Final Project Stage3

Final Project Stage 3, due lesson 38

Stage3 Assignment

38

Final Project Stage4

Stage4 Assignment

39

Final Project Stage4

Stage4 Assignment

40

Final Project Quiz (worth 2 quiz grades)

Final Project Stage 4, due lesson 40

Stage4 Assignment