Practice Problems (KEY)

Practice Problems (KEY)#

Problem 1.#

What components make up a DRAM bit cell?

A DRAM bit cell consists of:

  • One (1) transistor

  • One (1) capacitor

This structure is commonly referred to as a 1T1C cell (one-transistor, one-capacitor).

The capacitor stores the bit as electrical charge (charged = 1, discharged = 0), while the transistor acts as an access switch that connects the capacitor to the bitline during read and write operations.

Problem 2.#

Explain why DRAM exhibits slower access times than SRAM.

DRAM stores each bit as charge on a capacitor. Because real capacitors are not ideal, that charge gradually leaks over time.

As a result, DRAM cells must be periodically refreshed (rewritten) to restore the stored charge. Additionally, reading a DRAM cell is a destructive operation—the stored charge is disturbed during the read and must be rewritten afterward.

These refresh and restore operations increase access latency, making DRAM slower than SRAM.

Problem 3.#

Which type of memory is non-volatile?

Non-volatile memory retains stored data even when power is removed from the system.

In other words, if you power off your computer, non-volatile memory preserves its contents.

Examples include:

  • Read-Only Memory (ROM)

  • Flash Memory

  • Solid-State Drive (SSD) storage

Problem 4.#

The program shown below calculates the average of three numbers. After eight CPU cycles have executed, determine the values of the Instruction Register (IR), the accumulator, and RAM address 12.

Solution Walkthrough#

Let’s walk through the program carefully and track what happens at each step.

Step 1: Understand the Program#

From RAM:

Address

Instruction

0

LOAD 8

1

ADD 9

2

STORE 12

3

LOAD 12

4

ADD 10

5

STORE 12

6

LOAD 12

7

DIV 11

Data values:

  • RAM[8] = 8

  • RAM[9] = 2

  • RAM[10] = 11

  • RAM[11] = 3

Execute Step-by-Step#

We assume execution begins at address 0.

Cycle 1#

LOAD 8

\[ \text{ACC} \leftarrow \text{RAM}[8] = 8 \]

Accumulator = 8

Cycle 2#

ADD 9

\[ \text{ACC} \leftarrow 8 + \text{RAM}[9] = 8 + 2 = 10 \]

Accumulator = 10

Cycle 3#

STORE 12

\[ \text{RAM}[12] \leftarrow 10 \]

RAM[12] = 10

Cycle 4#

LOAD 12

\[ \text{ACC} \leftarrow \text{RAM}[12] = 10 \]

Accumulator = 10

Cycle 5#

ADD 10

\[ \text{ACC} \leftarrow 10 + \text{RAM}[10] = 10 + 11 = 21 \]

Accumulator = 21

Cycle 6#

STORE 12

\[ \text{RAM}[12] \leftarrow 21 \]

RAM[12] = 21

Cycle 7#

LOAD 12

\[ \text{ACC} \leftarrow 21 \]

Accumulator = 21

Cycle 8#

DIV 11

\[ \text{ACC} \leftarrow \frac{21}{\text{RAM}[11]} = \frac{21}{3} = 7 \]

Accumulator = 7

Final State After 8 Cycles#

  • Instruction Register (IR) = DIV 11

  • Accumulator = 7

  • RAM[12] = 21

Why this Makes Sense#

The program is computing:

\[ \frac{(8 + 2 + 11)}{3} = \frac{21}{3} = 7 \]

So the calculator is correctly computing the average of the three numbers.

Final Answer#

  • IR = DIV 11

  • Accumulator = 7

  • RAM[12] = 21

Problem 5.#

The assembly program shown below compares two numbers. After five CPU cycles have executed, determine the values of the Program Counter (PC), Instruction Register (IR), accumulator, and RAM address 8.

Additionally, determine the values of the Program Counter (PC) and Instruction Register (IR) at the beginning of the sixth CPU cycle.

Solution Walkthrough (After 5 CPU Cycles)#

Let’s step through the assembly program carefully and track the state of the machine.

Program Instructions#

Address

Instruction

0

LOAD 6

1

ADD 8

2

STORE 8

3

CMP 8, 9

4

JL 11

Data Values#

  • RAM[6] = 2

  • RAM[7] = 5

  • RAM[8] = (updated during program)

  • RAM[9] = 15

Step-by-Step Execution#

Cycle 1 — LOAD 6#

\[ \text{ACC} \leftarrow \text{RAM}[6] = 2 \]

Accumulator = 2

Cycle 2 — ADD 8#

At this point RAM[8] initially contains 5.

\[ \text{ACC} \leftarrow 2 + 5 = 7 \]

Accumulator = 7

Cycle 3 — STORE 8#

\[ \text{RAM}[8] \leftarrow 7 \]

RAM[8] is now 7

Cycle 4 — CMP 8, 9#

This compares:

  • RAM[8] = 7

  • RAM[9] = 15

Since:

\[ 7 < 15 \]

The “less than” condition is true.

No change to the accumulator during a compare operation.

Accumulator remains 7.

Cycle 5 — JL 11#

JL means Jump if Less.

Because the comparison indicated 7 < 15, the jump is taken.

\[ \text{PC} \leftarrow 11 \]

However, depending on the CPU model convention used in this course, the Program Counter may already have incremented during fetch, so the snapshot shows:

  • PC = 4

  • IR = JL 11

  • Accumulator = 7

  • RAM[8] = 7

Final State After 5 Cycles#

  • Program Counter (PC) = 4

  • Instruction Register (IR) = JL 11

  • Accumulator = 7

  • RAM[8] = 7

Beginning of the 6th Cycle#

Since the jump condition was satisfied, execution transfers to:

\[ \text{RAM}[11] = \texttt{END\_PROGRAM} \]

At the beginning of cycle 6:

  • PC = 11

  • IR = END_PROGRAM

Why This Makes Sense#

The program computes:

\[ 2 + 5 = 7 \]

It stores 7 into RAM[8], then checks whether 7 is less than 15.
Since it is, the jump to END_PROGRAM is taken.

The control flow behaves exactly as expected.

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